1. Field of the Invention
The present invention relates to insulated gate power transistor semiconductor devices, and to methods of making such devices.
2. Description of Related Art
Vertical insulated gate field effect power transistor semiconductor devices are known comprising a semiconductor body having an active area with a plurality of electrically parallel transistor cells, wherein each transistor cell has a source region and a drain region which are separated by a channel-accommodating body region adjacent a peripheral insulated gate structure.
Two types of such known vertical insulated gate power transistor devices are the double-diffused metal-oxide-semiconductor form of vertical MOSFET device (VDMOS), and the trench-gate form of vertical MOSFET device. In a VDMOS device the gate structure has a planar gate insulation layer on the top surface of the semiconductor body with the gate material thereon. In the on-state of this device current flows in each transistor cell from the source region laterally under the gate insulation layer in a conduction channel through the body regions into a peripheral drain drift region and then vertically through the drain drift region. In a trench-gate device the gate structure has a trench which extends vertically through the body region with a gate insulation layer at the vertical and bottom walls of the trench and gate material in the trench within the gate insulation. In the on-state of this device current flows in each transistor cell only vertically from the source region in a conduction channel next to the vertical gate insulation layer through the body region into a drain drift region.
A desirable property of power transistors is to have a low on-state resistance. Considering the two known power transistor devices just described, it is known that when both these device structures are used for low and medium voltage power transistors, that it is with a drain-source breakdown reverse voltage of up to respectively about 50 volts and about 200 volts, the on-state resistance of the device is to a large extent dependent on the sum total of the conducting channel peripheries. Thus for a given size of the device, that is a given active transistor cell area, a larger number of transistor cells in that active area leads to a lower on-state resistance. A limitation in this respect for the VDMOS device is that if the transistor cells are packed too close together by reducing the lateral extent of the peripheral drain drift region then the “Junction-FET” effect in this region will constrict the vertical current flow path down to the drain. The trench-gate device does not have this “Junction-FET” limitation, so that for a given size of device the trench-gate structure can have more transistor cells and a lower on-state resistance.
Another desirable property for power transistors is to have good switching performance, that is fast switching and low switching losses when the device is turned on and turned off. This is particularly important where the power transistor is to be used in the output stage of a power supply, for example a voltage regulation module (VRM), where it is continuously turned on and off at very high frequency. This good switching performance depends particularly on the device having a low gate-drain capacitance. A limitation in this respect for the trench-gate device is the contribution to gate-drain capacitance added by the gate insulation at the bottom of the trench. The VDMOS device does not have this added contribution to gate-drain capacitance.
Although both on-sate resistance and gate-drain capacitance are important as discussed above, the present invention is more particularly concerned with devices having the possibility of very low on-state resistance and so relates exclusively to trench-gate devices.
FIG. 1 of the accompanying drawings shows a schematic cross-section view of a known trench-gate form of vertical MOSFET power transistor semiconductor device 1. The device 1 comprises a silicon semiconductor body 10 with top and bottom major surfaces 10a, 10b, first conductivity type drain region 11 and a first conductivity type drain drift region 12.
FIG. 1 shows the lateral extent (the cell pitch) of one complete transistor cell TC and part of an adjacent transistor cell at either side of the cell TC. Two sections are shown of a peripheral insulated gate structure G located in a trench 20 at the boundary between each two adjacent transistor cells. The trench-gate structure G extends vertically through a channel-accommodating second, opposite, conductivity, type body region 23 into the drain drift region 12, and has silicon dioxide insulating material 21 at the vertical and bottom walls of the trench 20 and gate material 22 in the trench 20 within the insulating material 21. A source region 24, of the first conductivity type, is present in each transistor cell under the top major surface 10a and adjacent the trench gate 21, 22. Thus the source region 24 and the drain drift region 12 are vertically separated by the channel-accommodating body region 23 adjacent the trench-gate 21, 22 provided by the peripheral insulated gate structure G. This enables a vertical conduction channel 23a to be formed in the body portion 23 when a suitable gate potential is applied to the gate material 22 in the on-state of the device 1, whereby current flows in a path in each transistor cell from the source region 24 vertically through the conduction channel 23a to the drain drift region 12.
An insulating region 25 is provided over the gate structure G. Source metallisation 18 contacting all of the source regions 24 is provided on the first major surface 10a over the insulating region 25 to provide a source electrode S. Although not shown, electrical connection to the insulated gate structure G is provided by extending the insulating material 21 from the trenches 20 on to the top surface 10a of the semiconductor body 10 in an inactive area outside the active transistor cell area and extending the gate material 22 on to this top surface insulating layer where it is contacted by metallisation to provide a gate electrode. A metallisation layer 19 forms an ohmic contact with the drain region 11 so as to provide a drain electrode D.
The cross-section view shown in FIG. 1 applies equally to each of two cell geometries which are known for trench-gate devices. FIG. 2 of the accompanying drawings shows a plan view of an open-cell geometry having a one-dimensionally repetitive pattern in which the trench-gates G1 are parallel stripes which each extend across the active area of the device at the peripheries of open stripe-shaped transistor cells TC1. In this case FIG. 1 shows a cross-section view along the line II-II of FIG. 2. FIG. 3 of the accompanying drawings shows a plan view of a closed-cell geometry having a two-dimensionally repetitive pattern in which a network of trench-gates G2 over the active area of the device surrounds closed polygonal transistor cells TC2. In this case FIG. 1 shows a cross-section view along the line III-III of FIG. 3 in which the closed cells are square shaped. Another commonly used closed polygonal transistor cell is hexagonal shaped, a cross-section view of which would again be as shown in FIG. 1. FIGS. 2 and 3 show the active cell area dimensions of the transistor cells for both the open-cell and closed-cell geometries which are the trench width T, the semiconductor mesa width M between trenches and the cell pitch P which is the sum of T and M.
FIG. 4 of the accompanying drawings shows measurements which we have made comparing the specific on-state resistance Rds,on (mOhm.mm2) of an open stripe cell trench-gate device (curve 4A) and a closed square cell trench-gate device (curve 4B) as described with reference to FIGS. 1 and 3 over a range of cell pitches from 2 micron to 7 micron. In both cases the trench width is 0.4 micron at 2 micron cell pitch and about 0.6 micron for pitches greater than 2 micron, and the semiconductor material is {100} crystal orientation silicon. In these devices the channel-accommodating body region 23 extends vertically to approximately 0.7 micron below the upper surface 10a of the semiconductor body, the drain drift region 12 extends vertically to approximately 0.6 micron below the body region 23 and the trenches 20 are approximately 1.1 micron deep. The combination of the trench depth and the drain drift region depth are chosen to give a specified drain-source reverse breakdown voltage BVds for the device, in this case approximately 20 volts. The combination of the body region depth and the drain drift depth are chosen to give a low specific on-state resistance for the specified drain-source breakdown voltage of the device. It is to be noted that the body region and drain drift region vertical profiles are shallower, and the corresponding values for Rds,on shown in FIG. 4 are lower, than for currently commercially available devices.
FIG. 4 shows that, for the same cell pitch, the closed square cell devices have a lower specific on-state resistance than the open stripe cell devices. This is true down to about 2 micron cell pitch where the specific resistance is approximately equal for the two types of device. However, a further advantage of closed-cell devices compared with open-cell devices is that, particularly for low voltage devices, for a given cell pitch the specific on-state resistance for a closed cell device may be reduced by reducing the trench width whereas this is not possible for an open cell device. The reason for this is that for a closed cell device having a given cell pitch, reducing the trench width increases the channel perimeter and hence reduces the channel resistance; whereas for an open cell device reducing the trench width does not increase the channel perimeter. This possibility for reducing the specific resistance of closed cell devices is disclosed in International Patent Application published as WO-A-02/15254 (our reference PHNL010059), the contents of which are incorporated herein by reference, which also discloses a suitable method for producing narrow trenches in the range 0.4 micron to 0.1 micron; this method including forming a silicon nitride cup on the semiconductor body top surface, forming curved spacers of silicon dioxide within the nitride cup which are used to etch a window in the nitride cup and then etching a trench using the window in the nitride.
FIG. 5 of the accompanying drawings shows measurements which we have made comparing the drain-source reverse breakdown voltage BVds of an open stripe cell trench-gate device (curve 5A) with the BVds of a closed square cell trench-gate device (curve 5B) and a closed hexagonal cell trench-gate device (curve 5C) over a range of cell pitches from 2 micron to 7 micron. In all three devices the combination of the trench depth and the drain drift region depth dimensions is chosen to be the same as described above for the devices as measured in FIG. 4 to give a specified breakdown voltage BVds of 20 volts. Curve 5A shows that for the open stripe cell devices BVds has the specified value of 20 volts over the range of cell pitches, curve 5B shows that for the closed square cell devices BVds is reduced to about 17 volts over the range of cell pitches, and curve 5C shows that for the closed hexagonal cell devices BVds is further reduced to about 15 volts over most of the range of cell pitches. Considering the results shown in FIGS. 4 and 5, the breakdown voltage BVds could be increased for the closed cell devices by increasing the drain drift depth but this would also undesirably increase the specific resistance.
It is therefore desirable to increase the drain-source reverse breakdown voltage for closed cell trench-gate vertical power transistor semiconductor devices without increasing the specific on-state resistance as would occur in the manner mentioned just above. The invention seeks to address this issue using the inventors' appreciation of the properties of the corners of the transistor cells adjacent the intersection regions of the trench network for such closed cell devices, as will be discussed below.
FIGS. 6A and 7A of the accompanying drawings respectively show a plan view of part of a trench network of the closed square transistor cell device and of the closed hexagonal transistor cell device for which breakdown voltage BVds measurements have been shown in FIG. 5. As shown in FIG. 6A the trench network comprises a segment trench region STR1 adjacent each one of four sides of a transistor cell TCS and an intersection trench region ITR1 (shown shaded) adjacent each one of the four corners of the transistor cell TCS. As shown in FIG. 7A the trench network comprises a segment trench region STR2 adjacent each one of six sides of a transistor cell TCH and an intersection trench region ITR2 (shown shaded) adjacent each one of the six corners of the transistor cell TCH. The dotted square in FIG. 6A encloses the area around one of the intersection trench regions ITR1, this area is shown enlarged in FIG. 6B and a section view along the line I-I of FIG. 6B is shown in FIG. 6C. Likewise, the dotted triangle in FIG. 7A encloses the area around one of the intersection trench regions ITR2, this area is shown enlarged in FIG. 7B and a section view along the line I-I of FIG. 7B is shown in FIG. 7C. FIGS. 6C and 7C respectively show that the depth DI1, DI2 of the trench in the intersection regions is greater than the depth DS1, DS2 of the trench in the segment regions. An explanation for the trench depth effect as shown in FIGS. 6C and 7C is as follows. The trench networks shown in FIGS. 6A and 7A are each produced using a conventional process in which a mask pattern is provided for the whole trench network and there is one etching process for the whole network. In this case there is a loading effect which provides a more efficient supply and hence a greater concentration of the etch chemicals, with a resulting greater trench depth, at the intersection trench regions compared with the segment trench regions.
It will be noted that the intersection trench depth DI2 for the hexagonal closed cell device is shown in FIG. 7C to be greater than the intersection trench depth DI1 for the square closed cell device as shown in FIG. 6C. This will be the case if our following theory for the loading effect at the intersection trench regions is correct. This theory is that the loading effect is proportional to the number of segment trench regions at the periphery of an intersection trench region, four as shown in FIG. 6B and three as shown in FIG. 7B; and that the loading effect is inversely proportional to the area of an intersection trench region, T2 for the square region ITR1 shown in FIG. 6B where T is the trench width and 0.43T2 for the equilateral triangle region ITR2 shown in FIG. 7B where the trench width T is the same. We have made experimental observations using SEM photography which confirm qualitatively that the intersection trenches are deeper than the segment trenches for both the square cell network and the hexagonal cell network. However, the limitations of SEM photography have prevented us from measuring the areas of the intersection trench regions for both these networks and from quantitatively measuring the depths of the intersection trenches for both these networks, and so we have been unable to confirm whether our loading effect theory described above is correct.
FIG. 8A of the accompanying drawings shows a cross-section view along the line I-I of both FIGS. 6A and 7A, that is showing part of the closed transistor cell TCS/TCH and part of the segment trench region STR1/STR2 adjacent a side of the cell for both the square closed cell device and the hexagonal closed cell device. FIG. 8B of the accompanying drawings shows a cross-section view along the line II-II of both FIGS. 6A and 7A, that is showing part of the closed transistor cell TCS/TCH and part of the intersection trench region ITR1/ITR2 adjacent a corner of the cell. FIGS. 8A and 8B show the greater depth of the intersection trench regions ITR1/ITR2 compared with the depth of the segment trench regions STR1/STR2 as has been described above with regard to FIGS. 6B, 6C, 7B and 7C. The dashed lines in FIGS. 8A and 8B show the concentration of equi-potential lines, for the same applied voltages, respectively at the bottom corner BC1 of the segment trench region STR1/STR2 at a side of the cell TCS/TCH and at the bottom corner BC2 of the intersection trench region ITR1/ITR2 at the corner of the cell TCS/TCH. These equi-potential lines become closer at both bottom corners BC1 and BC2, but are closer at the bottom corner BC2 than at the bottom corner BC1 which implies a higher electric field at the corner BC2 than at the corner BC1. An open cell geometry device such as shown in FIG. 2 has trench bottom corners such as BC1 but does not have trench bottom corners such as BC2. The higher electric field at the cell corner bottom trench corner BC2 is a major factor contributing to the lower drain-source breakdown voltage BVds shown in FIG. 5 for the closed cell devices compared with the open cell device. Also, the greater depth of intersection trench regions ITR2 compared with the intersection trench regions ITR1 if it be the case, and the hexagonal cell having six corners compared with the square cell having four corners, are consistent with the breakdown voltage BVds being lower for the hexagonal cell device (curve 5C) than for the square cell device (curve 5B) as shown in FIG. 5.
Another factor, apart from the greater intersection trench depths, which contributes to lower drain-source reverse breakdown voltage BVds in closed cell geometry devices compared with open cell devices is that in operation, because the charge in the surrounding trench gate must be equal and opposite to the charge in the drain drift region for each transistor cell, there is a concentration of electric charge in the drain drift region at the corners of the closed cells compared with at the sides of the closed cells. This charge concentration leads to a higher electric field at the corners of the closed cells which is effective at the bottom corners of the intersection trench regions to lower the breakdown voltage BVds.
In FIGS. 8A and 8B the insulating material 21A2 at the vertical sides of the corners of the intersection trench regions ITR1/ITR2 is shown to have the same thickness as the insulating material 21A1 at the vertical sides of the segment trench regions STR1/STR2; the thickness of the insulating material 21B2 at the bottom of the intersection trench regions ITR1/ITR2 is shown to have the same thickness as the insulting material 21B1 at the bottom of the segment trench regions STR1/STR2; and the vertical side thicknesses 21A1/21A2 are the same as the bottom thicknesses 21B1/21B2. These equal insulating material thicknesses are according to conventional practice.
FIG. 8C of the accompanying drawings exemplifies and illustrates an embodiment of the present invention, having insulating material 21C at the bottom of the intersection trench regions ITR1/ITR2 with a thickness greater than that of the insulating material 21B1 at the bottom of the segment trench regions STR1/STR2. As shown in FIG. 8C, the spacing of the equi-potential lines near the bottom trench corner BC2 at the corner of the closed cell is increased as a result of the increased bottom insulation material thickness, thereby reducing the maximum electric field at this corner BC2 and thereby increasing the drain-source reverse breakdown voltage BVds of the device.
Some simulation results on a trench-gate MOSFET device are given below. We were not able to do real three-dimensional simulations, but only some two-dimensional (2D) simulations. These 2D simulations are valid for stripe open cell structures and also for ideal (no variation in trench depth at intersections) hexagon closed cell structures. However these simulations could only be qualitatively be interpreted for square cells in off-state (i.e. breakdown voltage) by examining several cross-sections in each location in the cell and examining the equi-potential lines at breakdown condition.
In the simulations we used the same vertical doping profiles as for the devices from which we obtained our experimental data as described with reference to FIGS. 4 and 5. Further, we assumed a pitch of 2.0 microns and a trench width of 0.4 μm. Also, we assumed a trench depth of 1.2 microns and basically imagined as if that is the actual depth of an intersection trench. The actual segment trench depth in the other part of the active area is 1.05 microns, measured by using SEM analysis. Also a gate-oxide thickness of 31 nm was used.
Some simulation results are shown in FIG. 9A of the accompanying drawings. This Figure shows the equi-potential lines in the device for a drain-source voltage of 17V. The breakdown voltage was here also 17V. We conveniently took half the pitch size since reflective boundary conditions (mirror) at the left and right edges are used in this device simulator. For the exactly the same device structure we increased the oxide thickness in the bottom of the device towards 0.35 micron, as shown in FIG. 9B of the accompanying drawings. The equi-potential lines are again taken for 17V drain-source voltage. The simulations predict that the breakdown voltage of this structure is 23V, which is higher than that of the structure shown in FIG. 9A. Consequently, when we have a locally deeper trench in the intersection areas than in the segment areas as shown in FIG. 9A, the breakdown voltage reduces from about 20V towards 17V. However, when we use a thick oxide in the bottom of the trench as shown in FIG. 9B the breakdown of the total device results in 20V again, because the breakdown voltage of the structure shown in FIG. 9B is 23V and is higher than that of the segment trench region. We did the same simulations for hexagonal structures and obtained the same results for breakdown voltages as discussed above. It will be noted that the simulation results patterns of equi-potential lines distribution shown in FIGS. 9A and 9B correspond well with the equi-potential line patterns shown respectively in FIGS. 8B and 8C.